View V3025_243598.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

R
EM MICROELECTRONIC-MARIN SA
V3025
Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming, User RAM and Battery Switch-over
Features
n Built-in quartz with digital trimming for frequency tuning and temperature compensation facilities n INTEL and MOTOROLA interface compatibility n 15 ns typical access time at 5.0 V n 1.2 mA typical standby current at 3.0 V n Wide supply voltage range, 2.0 VDD 5.5 V n Integrated battery switch-over n Battery voltage range, 2.0 VBAT 4.0 V n No busy state n No external components required n BCD format n Frequency measurements n Time set lock mode n Week number calculation n Clock counts up to 99 years n Leap year correction n 12 or 24 hour data format n Output programmable interrupts n Alarm interrupt, programmable up to one month n Timer interrupt, programmable up to 24 hours n Time to 1/100 of a second n To external time reference synchronisation n 50 Hz or nearest s/min synchronisation n Power fail input PFI n Power fail output or Reset output PFO n Tri-state bus capability when power fail (PFI = 0) n User RAM O n Temperature range - 40 to +85 C n Package SO28
Applications
n n n n n n Industrial controllers Alarm systems with periodic wake up PABX and telephone systems Point of sale terminals Automotive electronics Personal Computers
Typical Operating Configuration
VDD
VDD
Data Bus Address Bus
To Other Peripherals
Address AD0-7 WR RD CS
CPU
IRQ WR or R/W RD or DS VSS
R
Decoder
IRQ
A/D
WR
RD
CS
PFO V3025 in SO-28 PFI V VDD VBAT VSS OUT
RAM
VDD
VSS
100 nF
3.6 V
100 nF
Fig. 1
Description
The V3025 is a low power CMOS real time clock with an integrated battery switch-over. The standby current is typically 2.5 mA and the access time is 50 ns. The interface is a multiplexed address and data 8 bits bus. Multiplexing of address and data is handled by the input line A/D. There are no busy flags in the V3025, internal time update cycles are invisible to the user's software. Time data can be read from the V3025 in 12 or 24 hour data formats. An external signal puts the V3025 in standby mode. Even in standby, the V3025 pulls the IRQ pin active low on an internal alarm interrupt. Calendar functions include leap year correction and week number calculation. The V3025 can be synchronized to an external 50 Hz signal or to the nearest second or minute. The integrated battery switch-over supply the real time clock part by VDD as long as VDD is higher than VBAT. When VDD decreases under VBAT, the output PFO comes active and the real clock is supplied by the battery or the supercap.
Pin Assignment
SO28 SYNC PFI AD0 AD1 AD2 AD3 A/D IRQ VOUT VSS VSS VSS VSS VSS VBAT AD7 AD6 AD5 AD4 RD WR CS PFO VDD VDD VDD VDD VDD Fig. 2
V3025
1
Data
R
V3025
Absolute Maximum Ratings
Parameter
Maximum voltage at VDD and VBAT Max. voltage at remaining pins Min. voltage on all pins Maximum storage temperature Minimum storage temperature Maximum electrostatic discharge to MIL-STD-883C method 3015 Maximum soldering conditions Shock resistance
Handling Procedures
VSS + 7.0V VDD+ 0.3V VSS - 0.3V +125OC -550C 1000V 250OC x 10s 5000 g. 1 0.3ms, /2sine This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Symbol Conditions
VSUPmax VSUP Vmin TSTOmax TSTOmin VSmax TSmax
Operating Conditions
Parameter
Operating temperature Main supply votage Battery supply voltage Logic supply voltage Supply voltage dv/dt (power-up & down) Decoupling capacitor
Symbol Min. Typ. Max. Units
TA VDD VBAT VSUP dv/dt 100 -40 2 2 2.0 +85 5.5 4 5.0 5.5 6
O
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
C V V V
V/ms nF Table 2
Electrical Characteristics
VDD = 5.0V 10%, VBAT = 3 V, VSS = 0 V, TA = -40 to +85OC, unless otherwise specified
Parameter
Standby current
1)
Symbol
IDD1 IDD2 IBAT IDYN
Test Conditions
VDD = 3 V, VBAT = 0 V, PFI = 0 VDD = 5.5 V, PFI = 0 VDD = 0 V, PFI = 0 CS = 4 MHz, RD = VSS, WR = VDD IOL = 6 mA IOL = 1 mA, VDD = 2 V TA = +250C TA = +250C IOL = 6 mA IOH = 6 mA TA = +250C VILS= 0.8 V VSSMin.
Typ.
1.2 2.5 1.3
Max.
10 15 10 1.5
Units
mA mA mA mA
Standby current 2) Dynamic current IRQ (open drain) Output low voltage Output low voltage Inputs and Outputs Input logic low Input logic high Output logic low Output logic high PFI activation voltage PFI hysteresis Pullup on SYNC Input leakage Output tri-state leakage Oscillator Characteristics Starting voltage Frequency Characteristics Start-up time Frequency tolerance Frequency stability Temperature stability Aging Accuracy versus switch-over
1)
1)
VOL VOL VIL VIH VOL VOH VPFL VH ILS IIN ITS VSTA VSTA TSTA Df/f fsta tsta tag ASW
0.4 0.4 0.2 VSUP 0.8 VSUP 0.4 2.4 0.5 VDD 100 40 5 5
V V V V V V V mV mA nA nA V V s ppm ppm/V ppm ppm/year ppm Table 3
20
1000 1000
2 2.5 1 4) 210 1 see Fig. 6 0.2
TA = +25OC addr. 10 hex = 00 hex 3) 2.0 VDD 5.5 V addr. 10 hex = 00 hex o TA = + 25 C, first year VBAT = 3 V, 10 pulses of VDD switching between 2 to 5 V in 70 ms
150
251 5
5
With PFO = 0 (VSS) all I/O pads can be tri-state, tested. With PFO = 1 (VSUP), CS = 1 (VDD) and all other I/O pads fixed to VSUP or to VSS: same standby current, not tested. All other inputs to VDD and all outputs open.
3)
2)
At a given temperature.
4)
See Fig. 5
2
R
V3025
Switch-over Electrical Characteristics
TA = - 40 to 850C, inputs to VDD, outputs not connected, unless otherwise specified Parameter ON ON VDD VDD resistance of VDD to VOUT resistance of VBAT to VOUT voltage over VBAT for switching voltage under VBAT for switching Symbol Test Conditions RVDD RBAT VSVDD VSBAT TRDD TFDD VDD = 3V, VBAT = 0 V, IOUT =100mA VDD = 0V, VBAT = 3V, IOUT = 20mA VBAT= 3V, VOUT open VBAT = 3V, VOUT open VBAT = 3V, VDD rise from 2.8 V to 3.5V VBAT= 3V, VDD falling from 3.5 V to 2.8 V Min. Typ. 4 24 3.21 3.08 14 8 Max. 8 40 3.45 3.18 100 60 Units W W V V s s Table 4
3.00 2.98
VDD rising edge switching delay to PFO and VOUT VDD falling edge switching delay to PFO and VOUT
Timing Characteristics
VDD = 5.0 10%, VBAT = 0 V, VSS = 0 V, and TA = - 40 to +85C Parameter Chip select duration, write cycle Write pulse duration Time between two transfers 1) RAM access time 2) Data valid to Hi-impedance 3) Write data settle time 4) Data hold time Advance write time PF response delay Rise time (all inputs) Fall time (all inputs) 5) CS delay after A/D CS delay to A/D
1)
Symbol tCS tWR tW tACC tDF tDW tDH tADW tPF tR tF tA/Ds tA/Dt
Test Conditions
Min. 50 50 100
Typ.
Max.
Units ns ns ns ns ns ns ns ns ns ns ns ns ns Table 5
CLOAD = 50 pF 10 50 10 10
50 30
60 40
100 200 200 5 10
tACC starts from RD (DS) or CS, whichever activates last Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF 2) tDF starts from RD (DS) or CS, whichever deactivates first 3) tDW ends at WR (R/W) or CS, whichever deactivates first 4) tDH starts from WR (R/W) or CS, whichever deactivates first 5) A/D must come before a CS and RD or a CS and WR combination. The user has to guarantee this.
Typical VDD Current vs. Temperature
7 6 5
IDD[A]
4 3 2 1 0 -50 -25 VDD= 5.5 V, VBAT= 3 V V DD = 4 V, V BAT = 0 V VDD= 3 V, VBAT= 0 V 0 25 TA [C] 50 75 100
Fig. 3
3
R
V3025
Typical VBAT Current vs. Temperature
3.5 3.0
I BAT [A]
2.5 2.0 1.5 1.0 0.5 0.0 -50 VDD = 0 V -25 0
VBAT= 4 V VBAT= 3 V VBAT= 2 V
25 TA [ C]
0
50
75
100 Fig.4
Typical Frequency on IRQ
DF ppm F0 250 200 150 100 50 0 -50 -30 -10 10 30 50 70 90
Address 10 hex = 00 hex
TA [0C]
Fig. 5
Module Characteristic
DF F0 [ppm] -100 DF ppm 2 = - 0.038 O 2 (T - TO) 10% F0 C DF/FO = the ratio of the change in frequency to the nominal value expressed in ppm (It can be thought of as the frequency deviation at any temperature.) o = the temperature of interest in C T O = the turnover temperature (25 5 C) TO To determine the clock error (accuracy) at a given temperature, add O the frequency tolerance at 25 C to the value obtained from the formula above. TO - 100 TO - 50 TO TO+50 TO+100 O T [ C] Fig. 6
Frequency ratio [ppm]
ma x.
-200
-300
-400 Temperature [OC]
min
.
4
R
V3025
Typical VDD Switch Resistance vs. Temperature
7 6 VDD=2 V VDD=3 V VDD=5 V VDD=4 V
R DD [ ]
5 4 3 2 1 0 -50 VBAT=0 V -25 0 25 TA [ C]
0
50
75
100 Fig. 7
Typical Battery Switch Resistance vs. Temperature
35 30 VBAT=2 V VBAT=3 V VBAT=4 V
RBAT [ ]
25 20 15 10 5 0 -50 VDD=0 V -25 0
25 TA [ C]
0
50
75
100 Fig. 8
Timing Waveforms
Read Timing for Intel (RD and WR pulse) and Motorola (DS or RD pin tied to CS, and R/W)
tF CS tA/Ds A/D
tCS tR
tW
tA/Dt RD/DS tACC tDF DATA DATA VALID Fig. 9a
5
R
V3025
Intel Interface
Write Timing
tCS CS tA/Ds A/D RD tWR WR tDW DATA tDH Fig. 9b tA/Dt tW
DATA VALID
Write
CS RD WR A/D Valid Address Valid Data Fig. 9c
Data Bus D0 to D7
Read
CS RD WR A/D Valid Address Valid Data Fig. 9d
Data Bus D0 to D7
6
R
V3025
Motorola Interface
Motorola Write
tCS CS tA/Ds A/D DS tADW R/W tDW DATA tDH Fig. 9e tA/Dt tW
DATA VALID
Write
CS DS R/W A/D Data Bus D0 to D7
Valid Address
Valid Data Fig. 9f
Read
CS DS R/W A/D Data Bus D0 to D7
Valid Address
Valid Data Fig. 9g
7
R
V3025
General Block Diagram
VOUT Oscillator and Divider Chain 100 Hz Interrupt Logic IRQ PFO
VDD
8
VBAT
RTC Supply Voltage
+
Status Registers
Address / Data
CS WR RD SYNC PFI
Digital Trimming
IRQ
32768 Hz 1kHz
Control Block and Output Buffers
A/D
Status Registers Digital Trimming Register Clock Registers Alarm Registers Timer Registers 16 Byte User RAM Command Addreses
Oscillator INIB. Reg. INIB.RAM
:42/43
:32
:10
100 Hz
Timer
1/100 Sec. Min. Hour
:31 Timer RAM
Reset WR F0 F1
Trim Bus
INIT. Bit
Reset INIT
Alarm RAM
COMP
Reset WR F2 Reset WR F1
8
Reset Logic Write F0, F1, F2
Clock RAM
:10
100 Hz 1 Hz
Clock
1/100 Sec. Min. Hour Day Month Year W/D W #
Fig. 10
8
R
V3025
Pin Description
SO28 Package
Pin 1 2 3 4 5 6 7 8 9 10 - 14 15 - 19 20 21 22 23 24 25 26 27 28 Name Description SYNC PFI AD0 AD1 AD2 AD3 A/D IRQ VOUT VSS VDD PFO CS WR RD AD4 AD5 AD6 AD7 VBAT Time synchronization Power fail Bit 0 from MUX address / data bus Bit 1 from MUX address / data bus Bit 2 from MUX address / data bus Bit 3 from MUX address / data bus Address / data decode Interrupt request Switch-over output Supply ground (substrate) Positive supply terminal Power fail output Chip select WR (Intel) or R/W (Motorola) RD (Intel) or DS (Motorola) Bit 4 from MUX address / data bus Bit 5 from MUX address / data bus Bit 6 from MUX address / data bus Bit 7 from MUX address / data bus I I I/O I/O I/O I/O I O O GND PWR O I I I I/O I/O I/O I/O PWR
Table 6
Initialisation
When power is first applied to the V3025 all registers have a random value. To initialise the V3025, software must first write a 1 to the initialisation bit (addr. 2 bit 4) and then a 0. This sets the Frequency Tuning bit and clears all other status bits. The time and date parameters should then be loaded into the RAM (addr. 20 to 28 hex) and then transferred to the reserved clock area using the clock command followed by a write. The digital trimming register must then be initialised by writing 210 (D2hex) to it, if Frequency Tuning is not required. After having written a value to the digital trimming register the frequency tuning mode bit can be cleared.
RAM Configuration
The RAM area of the V3025 has a reserved clock and time area, a data space, user RAM and an address command space (see Table 10 or Fig. 10). The reserved clock and timer area is not directly accessible to the user, it is used for internal time keeping and contains the current time and date plus the timer parameters.
Data Space
All locations in the data space are Read/Write. The data space is directly accessible to the user and is divided into five areas : Status Registers - three registers used for status and control data for the device (see Table 7,8 and 9). Reserved bits must be set to 0. Digital Trimming Register - a special function described under "Frequency Tuning". Time and Date Registers - 9 time and date locations which are loaded with, either the current time and date parameters from the reserved clock area or the time and date parameters to be transferred to the reserved clock area. Alarm Registers - 5 locations used for setting the alarm parameters. Timer Registers - 4 locations which are loaded with either the timer parameters from the reserved timer area or the timer parameters to be transferred to the reserved timer area.
Battery supply
Functional Description
Power Supply, Data Retention and Standby
The V3025 is put in standby mode by activating the PFI input. When pulled logic low, PFI will disable the input lines, and immediately take to high impedance the lines AD 0-7. Input states must be under control whenever PFI is deactivated. If no specific power fail signal can be provided, PFI can be tied to the system RESET. Even in standby the interrupt request pin IRQ will pull to ground upon an unmasked alarm interrupt occurring.
Switch-over
The switch-over supplies the core of the RTC. The I/O pads are supplied by VDD, except for IRQ and SYNC. The SYNC input is internally pulled-up to VOUT, IRQ can be externally pulled-up between 2 and 5.5 V. The switch-over circuitry works in recovery mode. During switching, both transistors (VDD to VOUT and VBAT to VOUT) are ON. This is the guarantee that the RTC is always supplied. The power fail signal becomes active (PFO = 0) when VDD < VBAT (see Table 4).
User RAM
The V3025 has 16 bytes of general purpose RAM available for the users applications. This RAM block is located at addresses 50 to 5F hex and is maintained even in the standby mode (PFI active). The commands, or the time set lock bit, have no effect on the user RAM block. Reading or writing to the user RAM is similar to reading or writing to any system RAM address.
9
R
V3025
Status Words
Status 0 - Address 00 Hex 76543210 Read / Write bits 0 - disabled / 24 hour 1 - enabled / 12 hour frequency tuning mode pulse enable / disable alarm enable / disable timer enable / disable 1) 24 hour / 12 hour time set lock test bit 0 test bit 1 Table 7
RAM Map
Address Dec Hex Parameter Range
Status 1 - Address 01 Hex 76543210 Read / Write bits 0 - masked / no event 1 - unmasked / event pulse mask alarm mask timer mask reserved pulse flag alarm flag timer flag reserved Table 8
Status 2 - Address 02 Hex 76543210 Read / Write bits 0 - disabled 1 - enabled pulse every 10 ms pulse every 100 ms pulse every second pulse every minute initialisation bit SYNC 50 Hz SYNC second SYNC minute Table 9
Data Space Status 00 status 0 00 01 status 1 01 02 status 2 02 Special purpose 10 digital trimming 16 Clock 32 20 1/100 second 33 21 seconds 34 22 minutes 35 23 hours1) 36 24 date 37 25 month 38 26 year 39 27 week day 40 28 week number Alarm 1/100 second 30 48 31 49 seconds 32 50 minutes 1) 2) 33 51 hours date 34 52 Timer 40 64 1/100 second 41 65 seconds 42 66 minutes 43 67 hours User RAM 50 user RAM, byte 0 80 51 user RAM, byte 1 81 52 user RAM, byte 2 82 53 user RAM, byte 3 83 54 user RAM, byte 4 84 55 user RAM, byte 5 85 56 user RAM, byte 6 86 57 user RAM, byte 7 87 58 user RAM, byte 8 88 59 user RAM, byte 9 89 5A user RAM, byte 10 90 5B user RAM, byte 11 91 5C user RAM, byte 12 92 5D user RAM, byte 13 93 5E user RAM, byte 14 94 5F user RAM, byte 15 95 Address Comand Space 240 F0 clock and timer transfer 241 F1 clock transfer 242 F2 timer transfer
1)
0-255 00-99 00-59 00-59 00-23 01-31 01-12 00-99 01-07 00-53 00-99 00-59 00-59 00-23 01-31 00-99 00-59 00-59 00-23
Table 10
Address Command Space
This space contains the three commands used for carrying out the transfers between the Time and Date Register and / or the Timer Registers and the reserved clock and timer area.
The MSB (bit 7) of the hours byte (addr. 23 hex for the clock and 33 hex for the alarm) are used as AM/PM indicators in the 12 hour time data format and reading of the hours byte must be preceded by masking of the AM / PM bit. A set
10
R
V3025
AM/PM bit indicates PM. In the 24 hour time data format the bit will always be zero. 2) The alarm hours, addr. 33 hex, must always be rewritten after a change between 12 and 24 hour modes. space in the RAM. The function of these commands is to transfer data from the reserved clock and timer area to the RAM or to transfer data in the opposite direction, from the RAM to the reserved clock and timer area. The commands take place in two steps as do all other communications. The command address is sent with A/D low. This is followed by either a read (RD) or a write (WR), with A/D high, to determine the direction of the transfer. If the second step is a read then the data is transferred from the reserved clock and timer area to the RAM and if the second step is a write then the data that has already been loaded into the RAM clock and/or timer locations is transferred to the reserved clock and/or timer area.
Communication
Data transfer is in 8 bit parallel form. All time data is in packed BCD format with tens data on lines AD 7 - 4 and units on lines AD 3 - 0. To access information within the RAM (see Fig. 10) first write the RAM address, then read or write from or to this location. Fig. 11 shows the two steps needed. The lines AD 0 - 7 will be treated as an address when pin A/D is low, and as data when A/D is high. Pin A/D must not change state during any single read or write access. One line of the address bus (e.g. A0) can be used to implement the A/D signal (see "Typical Operating Configuration", Fig. 1). Until a new address is written, data accesses (A/D high) will always be to the same RAM address. Communication Sequence
Clock and Calendar
The time and date locations in RAM (see Table 10) provide access to the 1/100 seconds, seconds, minutes, hours, date, month, year, week day, and week number. These parameters have the ranges indicated in Table 10. The V3025 may be programmed for 12 or 24 hour time format (see section "12/24 Data Format"). If a parameter is found to be out of range, it will be cleared when the units value on its being next incremented is equal to or greater than 9 eg. B2 will be set to 00 after the units have incremented to 9 (ie. B9 to 00). The device incorporates leap year correction and week number calculation at the beginning of a year. If the first day of the year is day 05, 06 or 07 of the week, then it is given a zero week number, otherwise it becomes week one. Week days are numbered from 1 to 7 with Monday as day 1. Reading of the current time and date must be preceded by a clock command. The time and date from the last clock command is held unchanged in RAM. When transferring data to the reserved clock and timer area remember to clear the time set lock bit first.
A/D = 0
Write RAM address to the V3025
A/D = 1
Read or write data from or to the above address Fig. 11
Access Considerations
The communication sequence shown in Fig. 11 is re-entrant. When the address is written to the V3025 (ie. first step of the communication sequence) it is stored in an internal address latch. Software can read the internal address latch at any time by holding the A/D line low during a read from the V3025. So, for example, an interrupt routine can read the address latch and push it onto a stack, popping it when finished to restore the V3025. NB. Alarm and timer interrupt routines can reprogram the alarm and timer without it being necessary to read or reprogram the clock.
Timer
The timer can be used either for counting elapsed time, or for giving an interrupt (IRQ) on being incremented from 23:59:59:99 to 00:00:00:00. The timer counts up with a resolution of 1/100 second in the timer reserved areas. The timer enable / disable bit (addr. 00 hex, bit 3) must be set by software to allow the timer to be incremented. The timer is incremented in the reserved timer area, every internal time update (10 ms). The timer flag (addr. 01 hex, bit 6) is set when the timer rolls over from 23:59:59:99 to 00:00:00:00 and the IRQ becomes active if the timer mask bit (addr. 01, bit 2) is set. The IRQ will remain active until software acknowledges the interrupt by clearing the timer flag. The timer is incremented in the standby mode, however it will not cause IRQ to become active until power (VDD) has been restored. Note: The user should ensure that a time lapse of at least 60 microseconds exists between the falling edge of the IRQ and the clearing of the timer flag.
Commands
The commands allow software to transfer the clock and timer parameters in a sequence (eg. seconds, minutes, hours, etc.) without any danger of an internal time update with carry over corrupting the data. They also avoid delaying internal time updates while using the V3025, as updates occuring in the reserved clock and timer area are invisible to software. Software writes or reads parameters to or from the RAM only. There are three commands that occupy the command address
11
R
V3025
Reading the Clock
[Pin 7 = A/D] Start Write clock command (addr. F1 hex) to the V3025
Setting the Timer ( Time Set Lock Bit = 0)
[Pin 7 = A/D] Start Write 1/100 sec. address (40 hex) to the V3025 Write 1/100 sec. data to the RAM Write sec. address (41 hex) to the V3025 Write sec. data to the RAM Write min. address (42 hex) to the V3025 Write min. data to the RAM Write hours address (43 hex) to the V3025 Write hours data to the RAM Write timer command (addr. F2 hex) to the V3025 Write F2 hex to the V3025 to copy the timer parameters from RAM to the reversed timer area End
A/D = 0
A/D = 0
A/D = 1
Read data from the V3025 to copy the timer parameters from the reversed clock area to the RAM. A data read has no significance
A/D = 1
A/D = 0
A/D = 1 A/D = 0 Write 1/100 sec. address (20 hex) to the V3025 A/D = 0 A/D = 1 Read 1/100 sec. data from the RAM Write sec. address (21 hex) to the V3025 Read sec. data from the RAM Write min. address (22 hex) to the V3025 Read min. data from the RAM End A/D = 1
A/D = 1
A/D = 0
A/D = 0
A/D = 1
A/D = 1
A/D = 0
A/D = 0
A/D = 1
Fig. 12
Fig. 13 Note : Commands are only valid as commands when the A/D line is low. Writing F2 hex with the A/D line high, as in the last box of Fig.11, serves only to activate the V3025 write pin which determines the direction of transfer.
12
R
V3025
Alarm
An alarm date and time may be preset in RAM addresses 30 to 34 hex. The alarm function can be activated by setting the alarm enable / disable bit (addr. 00 hex, bit 2). Once enabled the preset alarm time and date are compared, every internal time update cycle (10 ms), with the clock parameters in the reserved clock area. When the clock parameters equal the alarm parameters the alarm flag (addr. 01 hex, bit 5) is set. If the alarm mask bit (addr. 01 hex, bit 1) is set, the IRQ pin goes active. The alarm flag indicates to software the source of the interrupt. IRQ will remain active until software acknowledges the interrupt by clearing the alarm flag. If the alarm is enabled, and an alarm address set to FF hex, this parameter is not compared with the associated clock parameter. Thus it is possible to achieve a repeat feature where an alarm occurs every programmed number of seconds, or seconds and minutes, or seconds, minutes and hours. The V3025 pulls the open drain IRQ line active low during standby when an alarm interrupt occurs. If the 12/24 hour mode is changed then the alarm hours must be re-initialised. Note: The user should ensure that a time lapse of at least 60 microseconds exists between the falling edge of the IRQ and the clearing of the alarm flag. bits 5 to 7 at addr. 02 hex, in accordance with Table 9. If more than one bit is set then all the synchronization bits are disabled. If the SYNC input is set low for longer than 200 ms, while in the synchronization mode, the clock will synchronize to the falling edge of the signal. Synchronization to the nearest second implies that the 1/100 seconds are cleared to zero and if the contents were > 50, the seconds register is incremented. Synchronization to the nearest minute implies that the seconds are cleared to zero and if the contents were > 30, the minutes register is incremented. Fractions of seconds are cleared.
Pulse
There are 4 programmable pulse frequencies available on the V3025, these are every 10 ms, 100 ms, second or minute. The pulse feature is activated by setting the pulse enable / disable bit at address 00, bit 1. The pulse frequency is selected by setting one of the bits 0 to 3 at address 02 hex (see Table 9). If more than one of the pulse bits are set then the feature is disabled. At the selected interval the pulse flag bit (addr. 01 hex, bit 4) is set. If the pulse mask bit (addr. 01 hex, bit 0) is set then the IRQ pin goes active. The pulse flag indicates to software the source of the interrupt. IRQ will remain active until software acknowledges the interrupt by clearing the pulse flag. The pulse feature is disabled while in standby. Upon power restoration the pulse feature is enabled if enabled prior to standby. See also the section "Frequency Tuning". Note: The user should ensure that a time lapse of at least 60 microseconds exists between the falling edge of the IRQ and the clearing of the pulse flag.
IRQ
The IRQ output is used by 4 of the V3025's features. These are: 1) Pulse, to provide periodic interrupts to the microprocessor at preprogrammed intervals; 2) Alarm to provide an interrupt to the microprocessor at a preprogrammed time and date; 3) Timer, to provide an interrupt to the microprocessor when the timer rolls over from 23:59:59:99 to 00:00:00:00; and 4) Frequency trimming (see section "Frequency Trimming"). The first 3 features listed are similar in the way they provide interrupts to the microprocessor. Each of the 3 has an enable / disable bit, a flag bit, and an interrupt mask bit. The enable / disable bit allows software to select a feature or not. A set flag bit indicates that an enable feature has reached its interrupt condition. Software must clear the flag bit. The interrupt mask bit allows or disallows the IRQ output to become active when the flag bit is set. The IRQ output becomes active whenever any interrupt flag is set which also has its mask bit set. For all sources of maskable interrupts within the V3025, the IRQ output will remain active until software clears the interrupt flag. The IRQ output is the logical OR of all the unmasked interrupt flags. The IRQ output is open drain so an external pullup to VDD is needed. In standby (PF active) the IRQ output will be active if the alarm mask bit (addr. 01 hex, bit 1) is set and the alarm flag is also set. The timer or the pulse feature cannot cause the IRQ output to become active while in standby.
Time Set Lock
The time set lock control bit is located at address 00 hex, bit 5 (see Table 7). When set by software, this bit disables any transfer from the RAM to the reserved clock and timer area as well as inhibiting any write to the digital trimming register at address 10 hex. When the time set lock bit is set the following transfer operations are disabled: The clock command followed by write, the timer command followed by write, the clock and timer command followed by write, and writing to the digital trimming register. A set bit prevents unauthorized overwriting of the reserved clock and timer area. Reading of the reserved clock and timer area, using the commands, is not affected by the time set lock bit. Clearing the time set lock bit by software will re-enable the above listed commands. On initialisation the time set lock bit is cleared. The time set lock bit does not affect the user RAM (addr. 50 to 5F hex).
Frequency Tuning
The V3025 offers a key feature called "Digital Trimming", which is used for the clock accuracy adjustment. Unlike the traditional capacitor trimming method, which tunes the crystal oscillator, the digital trimming acts on the divider chain, allowing the clock adjustment by software. The oscillator frequency itself is not affected.
Synchronization
There are 3 ways to synchronize the V3025. It can be synchronized to 50 Hz, the nearest second, or the nearest minute. Synchronization mode is selected by setting one of the
13
R
V3025
The Principle of Digital Trimming
With the digital trimming disabled (i.e. digital trimming register set to 00 hex), the oscillator and the first stages of the divider chain will run slightly too fast (typ. 210 ppm: ppm = parts per million), and will generate a 100 Hz signal with a frequency of typically 100.021 Hz. To correct this frequency, the digital trimming logic will inhibit every 31 seconds, a number of clock pulses, as set in the digital trimming register. Since the duration of 31 seconds corresponds to 1'015'808 oscillator cycles, the digital trimming has a resolution of 0.984 ppm. In other words every increment by 1 of the digital trimming value will slow down the clock by 0.984 ppm, which permits the accuray of 0.5 ppm to be reached. Note that a 1 ppm error will result in a 1 second difference after 11.5 days, or a 1 minute difference after 694 days! The trimming range of the V3025 is from 0 to 251 ppm. The 251 ppm correction is obtained by writing 255 (FFhex) into the digital trimming register. How to Determine the Digital Trimming Value The value to write into the digital trimming register has to be determined by the following procedure: 1. Initialise the V3025 by writing a 1 and then a 0 into the "Initialisation Bit" of the status register 2 (addr. 02 hex, bit 4). This activates the frequency tuning mode in status register 0 (addr. 00 hex, bit 1) and clears the other status bits. 2. Write the value 00 hex into the digital trimming register (addr. 10 hex). From now, the IRQ output (open drain) will deliver the 100 Hz signal, which has a 20% duty cycle. 3. Measure the duration of 21 pulses at the IRQ output, with the trigger set for the falling edge. It is possible also to divide the IRQ frequency by 21, using a TTL or CMOS external circuit. 4. Compute the frequency error in ppm:
6 210 ms - measured value in ms x 10 210 ms 5. Compute the corrective value to write into the digital trimming register. Digital trimming value = frequency error / 0.984 6. Write this value into the digital trimming register. 7. Switch off the frequency tuning mode in status 0 (addr. 00 hex, bit 0 set to 0). The Real Time Clock circuit will now run accurately at an operating temperature equal to the calibration temperature. If the operating temperature differs from the one at calibration time, the graphs shown on Fig. 5 and 6 will help in determining the definitive value. If the mean operating temperature of the equipment is not known at calibration time, the equipment user will do the final correction with a software provided by the system designer. To avoid the calibration procedure, it is possible also to set the digital trimming register to 210 (D2 hex) as a standard starting value, and let the final equipment user perform the final adjustment on site, which will take the real temperature into account.
(210 - 209.97) / 210 x 1E + 06 = 142.857 ppm. The value for the digital trimming register is: 142.857 / 0.984 = 145.18, rounded to 145 ppm (91 hex).
Time Correction with Change of Temperature
If the mean temperature on site is known to be 45 C, the frequency error determined at room temperature has to be modified, using the graphs or the equation on Fig. 6. Df/f = - 0.038 x (45 - 25) = 15.2 ppm 0 The trimming value for 45 C will be
(142.857 ppm - 15.2 ppm) / 0.984 = 129.73, rounded to 130 (82 hex).
2
o
12 / 24 Hour Data Format
The V3025 can run in 12 hour or 24 hour data format. On initialisation the 12/24 hour bit ad addr. 00 bit 4 is cleared putting the V3025 in 24 hour data format. If the 12 hour data format is required then bit 4 at addr. 00 must be set. In the 12 hour data format the AM/PM indicator is the MSB of the hours register addr. 23 bit 7. A set bit indicates PM. When reading the hours in the 12 hour data format software should mask the MSB of the hours register. In the 24 hour data format the MSB is always zero. The internal clock registers change automatically between 12 and 24 hour mode when the 24/12 hour bit is changed. The alarm hours however must be rewritten.
Test
From the various test features added to the V 3025 some may be activated by the user. Table 7 shows the test bits. Table 11 shows the three available modes and how they may be activated. The first accelerates the incrementing of the parameters in the reserved clock and timer area by 32. The second causes all clock and timer parameters, in the reserved clock and timer area, to be incremented in parallel at 100 Hz with no carry over, ie. independently of each other. The third test mode combines the previous two resulting in parallel incrementing at 3.2 kHz. While test bit 1 is set (addr. 00 hex, bit 7) the digital trimming action is disabled and no pulses are removed from the divider chain. Test bit 0 (addr. 00 hex, bit 6) can be combined with digital trimming (see section "Frequency Tuning"). To leave test, the test bits (addr. 00 hex, bits 6 and 7) must be cleared by software. Test corrupts the clock and timer parameters and so all parameters should be re-initialised after a test session. Test Modes
Addr. Addr. 00hex bit 7 00hex bit 6 0 0 1 0 1 0 Function Normal Operation Acceleration by 32 Parallel increment of all clock and timer parameters at 100 Hz with no carry over; dependent on the status of bit 3 at address 00 hex Parallel increment of all clock and timer parameters at 3.2 kHz with no carry over; dependent on the status of bit 3 at address 00 hex
freq. error =
Time Correction at Room Temperature
Let us consider that the duration of 21 pulses of the IRQ signal is 209.97 ms at room temperature. The frequency error is:
1
1
Table 11
14
R
V3025
Typical Operating Configuration
CPU
Data Bus Address Bus
IRQ WR or R/W RD or DS
WR
IRQ AD0 to AD7
A/D
CS
VDD 2.3 to 26 V Power supply Input VSS Output RES
Address Decorder VDD VSS
RD
PFO
RD
VSS
VDD
VSS
V3025
RAM
VDD VSS
VBAT VOUT PFI
A6300
WR
CS
Fig. 14
Process Application
Temperature sensor Controller Solenoid valve Fig. 15
- The formula in Fig. 5 is used by software to continually update the digital trimming register and so compensate the V 3025 for the ambient temperature. - The timer is used to measure the duration the valve is on. - The alarm feature is used to turn the controller power on and off at the time programmed by software. The V3025 pulls IRQ active low on an alarm even in standby and thus can control the power on/off switch for the controller.
Typical Applications
V 3025 Interfaced with Intel CPU (RD and WR pulse)
A/D Bus 0 - 7
Address Address Bus 0 - 7 Latch A0 to other peripherals and memory
CPU
Address Bus A8 - A15 Decoder
WR RD CS RD WR D 0 -7 A/D Fig. 16
V3025
15
R
V3025
V 3025 Interfaced with Motorola CPU (DS or RD pin tied to CS, and R/W)
Data Bus
CPU
Address Bus A0 Decoder
R/W DS RD CS A/D WR AD 0-7
to other peripherals and memory
V3025
Fig. 17
Ordering and Package Information
Dimensions of 28-Pin SOIC Package D h x 45 A A1 H a C L Dimensions in mm A A1 B C D E e H h L a Min. Nom. Max. 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 1.27 10.00 10.65 0.25 0.75 0.40 1.27 0 8 Fig. 18 Ordering Information When ordering, please specify the complete part number. Part Number V3025SO28B V3025SO28A Package 28-pin SOIC 28-pin SOIC Delivery Form Tape & Reel Stick Package Marking (first line) V3025A 28SI V3025A 28SI
28
27
26
17
16
15
E
1 2 3 12 13 14
e
B
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
O 2002 EM Microelectronic-Marin SA, 03/02, Rev. E/385
EM MICROELECTRONIC-MARIN SA, CH-2074 Marin, Switzerland, Tel. +41 - (0)32 75 55 111, Fax +41 - (0)32 75 55 403
WWW..COM
Copyright (c) Each Manufacturing Company. All Datasheets cannot be modified without permission.
This datasheet has been download from : www..com
100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www..com

▲Up To Search▲

Price & Availability of V3025

	To Download V3025 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .